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Personal Supercomputers:
Design, Application

Lviv Polytechnic National University Publishing, 2013
Authors: Anatoliy Melnyk, Viktor Melnyk

Personal Supercomputers: Architecture, Design, Application

Chameleon ©
A new C2HDL tool
from Intron ltd

On August 2014 Intron ltd
released an improved version of Chameleon ©

Intron ltd

in the NESUS Action

Improvement of heterogeneous
systems efficiency using
self-configurable FPGA-based computing


What is the Self-Configurable Computer System?

The self-configurable computer system is a computer system with reconfigurable logic, where program compilation includes automatically performed actions of creation of the configuration, and which acquires of that configuration automatically in the time of program loading for execution.

SCCS benefits

Ensured effective use of reconfigurable logic to perform arbitrary tasks

Loading of executable files and configuration files into computer's main memory and into reconfigurable logic is respectively performed by the operating system after program initialization.

Shortened information processing time

All actions, starting from the load balancing and till obtaining the executable file and the configuration files, are executed automatically at the stage of program compiling without user intrusion.

Reduced information processing complexity

Requirements to the user experience are simplified up to the knowing of high level programming language.

Simplified programming

The user uses ANSI C language that requires no additional constructions (parallel operators, directives etc.) and works with SCCS same as with conventional PC.

Introduction to the Self-Configurable Computer Systems

Computer systems performance is today improved with two major approaches: general-purpose computers’ computing power increase (creation of multicore processors, multiprocessor computer system, supercomputers), and adaptation of the computer’s hardware to the executed algorithm (class of algorithms). Last approach often provides application of hardware accelerators – ASIC-based and FPGA-based, also named reconfigurable, and is characterized by better performance / power consumption ratio and lower cost as compared to the general-purpose computers of equivalent performance. However, such systems have typical problems.

The ASIC-based:

  1. they are effective only for certain classes of algorithms;
  2. for effective application there is a need to adapt algorithms and software.

The FPGA-based accelerators and reconfigurable computer systems (that use FPGAs as a processing units):

  1. the need in the process of writing a program to perform computing tasks balancing among the general-purpose computer and FPGA;
  2. the need of designing application-specific processors soft-cores;
  3. they are effective only for certain classes of problems, for which application-specific processors soft-cores were previously developed.

We work on creation of a new type of high-performance computer systems, which are named self-configurable FPGA-based computer systems (SCCS), and which are deprived of specified challenges. The goal of the SCCS is improvement of FPGA-based high-performance computer systems efficiency.

The aim of this site - to show the background of SCCS creation, current results of our research, and introduce some ongoing works on SCCS development.

The project titled "Improvement of heterogeneous systems efficiency using self-configurable FPGA-based computing" that is the part of the NESUS Action, is one of the projects being developed in direction of the SCCS creation.

SCCS Background

SCCS creation is the result of years of engineering and research work of our research group in the field of application-specific processors development their ASIC- and FPGA-implementation, and the creation of methods and means for their high-level design.

The background of SCCS is built on:

  1. Our ESL Design Tools and Solutions (developed in cooperation with Intron ltd:
    • Chameleon - System-Level Design Solution intended for ASIC design automatic generation from the algorithm described on ANSI C language.
    • OSCAR - System-Level Design Solution intended for an ASIC design automatic generation from the algorithmic representation.
    • IP Cores Generators:
      • FFT IP Cores Generators.
      • DES IP Cores Generators.
  2. Our new computer architecture
  3. Our new multiport computer memory with parallel conflict-free access to data.